Daniil Gentili - Project news

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Daniil Gentili - Project news

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The basic integer instruction sets are: - RV32I (32 registers, basic 32-bit integer instructions, control instructions (branch/jmp), load/store memory instructions, syscalls, memory ordering instructions (fences to avoid issues with out-of-order execution)) - RV32E (RV32I with 16 registers instead of 32) - RV64I (RV32I with 64-bit integer instructions and address space) - RV128I (RV64I with 128-bit integer instructions and address space)

685 03 JunЧитать пост →

Daniil Gentili - Project news

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Even atomics are a separate optional extension "A" (which makes sense as the basic RISC-V instruction set without any extension is very simple, and can for example be used on microcontrollers, there's even a simplified subset of the basic instruction set with fewer registers called RV32E)

601 03 JunЧитать пост →

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Fun fact: the basic RISC-V instruction set (both 32-bit and 64-bit variants) doesn't even implement multiplication and division, they're implemented in a separate optional extension "M", unlike other RISC instruction sets like ARM

599 03 JunЧитать пост →

Daniil Gentili - Project news

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Fun fact: the basic RISC-V instruction set (both 32-bit and 64-bit variants) doesn't even implement multiplication and division, they're implemented in a separate optional extension "M", unlike other RISC instruction sets like ARM

616 03 JunЧитать пост →

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Just in case you were curious, I'm reading the RISC-V spec because I'm working on a riscv64 implementation of JIT for PHP ;)

630 03 JunЧитать пост →

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Also it's funny how the HINT instructions don't have a custom opcode, and instead reuse the opcode of common instructions like ADD, SUB, with destination register x0 (aka all instructions writing to the register equivalent of /dev/null may be treated as microarchitectural performance hints by implementations that support performance hinting)

689 03 JunЧитать пост →

Daniil Gentili - Project news

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I get that they needed to simplify the hardware implementation but damn

599 03 JunЧитать пост →

Daniil Gentili - Project news

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RISC-V instruction encoding is insane: Yes, *please* encode the 12-bit immediate imm by putting bit 12 in bit 31, bits 10-5 in bits 30-25, bits 4-1 in bits 11-8 and bit 11 in bit 7

646 03 JunЧитать пост →

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MadelineProto now offers a simple broadcast API, that can be used to asynchronously broadcast messages to all users of a bot or userbot in the background, without incurring in timeouts or other issues. Note that unlike the bot API, MadelineProto can be used to fetch the full list of users, chats and channels of a normal bot, simply using its bot token. Here's a simple example, explaining how to broadcast a message and a photo to every user of a bot:

556 02 JunЧитать пост →

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